The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device having a plurality of reset circuits connected to a data bus pair.
As is well known, a semiconductor memory device generally comprises a memory cell array, a row decoder coupled to the memory cell array through word lines, an address buffer coupled to the row decoder, a sense amplifier and input/output gate coupled to the memory cell array through bit line pairs, a column decoder coupled to the sense amplifier and input/output gate, an address buffer coupled to the column decoder, input and output buffers coupled to the sense amplifier and input/output gate through a data bus pair, and the like. The data bus pair is reset to a reset voltage before each read operation. For example, the reset voltage is selected to a power source voltage, a ground voltage or an intermediate voltage between the power source and ground voltages.
Conventionally, a reset circuit resets the data bus pair to the reset voltage at one end of the data bus pair in a vicinity of the output buffer. However, the data bus pair can be described by an equivalent circuit which is essentially an RC circuit comprising distributed resistances and parasitic capacitances. For this reason, although the data bus pair is reset to the reset voltage relatively quickly at the one end in the vicinity of the output buffer, the other end of the data bus pair is only reset to the reset voltage after a time delay caused by the distributed resistances and the parasitic capacitances of the data bus pair.
The connection of the next selected bit line pair to the data bus pair can only be carried out after the resetting of the data bus pair is completed. Hence, the conventional memory device suffers a problem in that the access time to the memory device is long because the resetting of the data bus pair is slowed down by the distributed resistances and the parasitic capacitances of the data bus pair.
On the other hand, a noise which enters the data bus pair in the vicinity of the output buffer can be eliminated by the reset circuit when the data bus pair is reset to the reset voltage. However, when the noise enters the data bus pair on the other end from the output buffer, the elimination of the noise is also delayed because of the distributed resistances and the parasitic capacitances of the data bus pair. Thus, there is a problem in that the connection of the next selected bit line pair to the data bus pair can only be carried out after the resetting of the data bus pair is completed and after the noise is completely eliminated.